The present invention relates to integrated circuits in general and, in particular, to programmable input/output functionality for clock circuitry.
One of the critical success factors in the design and development of integrated circuits is the ability to adapt to new functional requirements in next generation electronic products quickly. Traditional ways to reduce the time it takes to introduce new products is to increase the available development resources and subdivide tasks to perform them in parallel. Additionally, circuits can be designed in anticipation of future requirements so that they can be reconfigured quickly. Known reconfigurable architectures include masked ROM, gate-arrays and analog arrays where logic, memory content or analog building block interconnect and attributes can be changed by modifying a subset of the normal process layers, typically the metal interconnect layers.
The introduction of non-volatile programming technology such as Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and One-Time-Programmable antifuse (OTP), allowed this reconfiguration to be done through electrical programming rather than wafer fabrication reticle changes. Such electrical programmability requires the use of passive and/or active switches to reconfigure the signal path. While the non-volatile memory technology has provided some flexibility in implementing reconfigurable ICs, a cost effective technique which enables a high level of configurability without consuming significant amounts of power and silicon real estate has not yet been disclosed.